Some data storage systems, such as Solid-State Drives (SSD), store data in a group of non-volatile memory devices such as Flash devices. Several techniques for controlling power consumption in such data storage systems have been proposed in the patent literature. For example, U.S. Patent Application Publication 2007/0159907, whose disclosure is incorporated herein by reference, describes a multi-chip package comprising a plurality of memory chips, each of the memory chips comprising an internal circuit, and a power level detector for detecting a level of a power supply voltage to initialize the internal circuit at power-up. The power level detectors in the respective memory chips are configured to initialize corresponding internal circuits at different points of time.
As another example, U.S. Pat. No. 7,200,062, whose disclosure is incorporated herein by reference, describes a dynamic random access memory device that includes a mode register that is programmed with a delay value. In some embodiments, an offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously.
U.S. Patent Application Publication 2004/0160842, whose disclosure is incorporated herein by reference, describes a semiconductor memory device including a plurality of memory chips. The memory chips are divided into first and second groups that are operated in parallel with each other at the time of a data read. Timings of activating sense amplifiers belonging to the first and second groups are made different from each other. Accordingly, the maximum value of peak current generated when the sense amplifiers are activated at the time of a data read is reduced by half in the semiconductor memory device as a whole.
U.S. Pat. No. 4,768,171, whose disclosure is incorporated herein by reference, describes a semiconductor memory circuit, which includes two or more memory cell arrays each having a plurality of memory cells. A peripheral circuit for achieving selective access operation is provided for each array. At least a timing signal and its delayed timing signals are generated in response to a control signal. Both of the timing signal and the delayed timing signal are used to enable the peripheral circuits at different timing.